CARTESI'S BOARD AND PROCESSOR

With Me Again, Tamara. I will tell you about this project.

Cartesi is a platform that has a mission to help the developer of Dapp to build the product become more compelling for clients. The core of Cartesi makes easy developer to leverage before existing knowledge and tools. Both of them have the function to boost their productivity. Cartesi is a paradigm shift like blockchain that brings the risk of the invention and real innovation. There is some component of Cartesi can help the developer to build creativity they take advantage of blockchain. Cartesi spread into two types.

A. The first type of Cartesi is the board. There is interaction from the board and processor in the device to physical address places. The 64KiB begins to address 0x1000 in the place where execution starts. The role of 64KiB ROM is to hold a device tree. It is describing the system of hardware. There are additional features from the ROM base to set the register of x10 to zero, x11 to device-tree. Besides that, it can jump to RAM base in the 0x80000000. It is the place where the entry point is residing.

In the Cartesi, physical memory is described by PMA. What is PMA? PMA is derived from the Physical Memory Attribute record. Some of the additional ranges can set for memory devices. The board of Cartesi support around thirty-two PMAs, read-only, available, and begin to offset 2KiB in physical memory. There is also future use around 2KiB. PMAs 16-23 describes as flash device 0-7, and PMA 0 describe RAM. PMAs are user-configurable and read-only. All of those record bound is the maximum amount of storage in the computation. Every Physical Memory Attribute record or PMA has two 64-bit words. The word is the start of range and length. The ranges are aligning with four KiB boundaries.

B. The second type of Cartesi is the processor. It is the implementation of RV64IMASU ISA. That was the extension. Cartesi machines offer Sv48 modes of memory and translation protection. It gives a 48bit virtual address space and then divides into 4KiB and arranged by 4 levels of the page table. This feature is a balance in the simplicity in the blockchain implementation. Cartesi has flexibility expected from the off-chain computation.

Cartesi specific name registers and follows semantics. The layout of I register has a privilege level. There is a condition where I am set to 1 when the processor is waiting for interrupts. There is also a condition where H becomes 1 in the signal of the processor. The processor has 512 byte that consists of 64 registers. All of them have 64 bits. The register is defined by RISC-V ISA, and the rest is Cartesi specific. It makes the state available, read-only, and externally. There is the technology of mapping in the individual register to 512 bytes in physical memory. Four level pages in the Cartesi created features to make balance the compromise between computation and blockchain implementation. There is ninety-nine instruction, twenty-eight is narrow. A fact that only complex operation is the virtual address for translation. This is so easy to use.

For more information, please follow these resources:

Official Website: https://cartesi.io/
Whitepaper: https://cartesi.io/cartesi_whitepaper.pdf
Facebook: https://www.facebook.com/cartesiproject
Twitter: https://twitter.com/cartesiproject
Telegram: https://t.me/cartesiproject
Medium: https://www.medium.com/cartesi
Profile Bitcointalk: https://bitcointalk.org/index.php?action=profile;u=1116890
Username: araalfaris
Email: tamaraalfaris@gmail.com